In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability.
Charge-domain circuits are implemented as charge-coupled devices (CCDs), as Metal Oxide Semiconductor (MOS) bucket-brigade devices (BBDs), and as bipolar BBDs. The present invention pertains primarily to MOS BBDs; it also has application to CCDs, in the area of charge-packet creation. Note that all circuits discussed below assume electrons as the signal-charge carriers, and use N-Channel Field Effect Transistors (NFETs) or N-channel CCDs for signal-charge processing. The identical circuits can be applied equally well using holes as charge carriers, by employing PFETs or P-channel CCDs and with reversed signal and control voltage polarities.
In MOS BBDs the charge packets are stored on capacitors. Charge transfer from one storage capacitor to the next occurs via a FET connected in common-gate configuration. The process of charge transfer in a BBD is explained with the aid of FIG. 1 and FIG. 2. These figures omit many practical details, but they suffice to show the essential features of charge transfer in conventional BBDs.
FIG. 1 shows the essential circuit elements for a BBD-type charge transfer. In FIG. 1 VX is an input voltage applied to the first terminal of capacitor 1. The second terminal of capacitor 1 and the source terminal of FET 2 are connected at node 4. The gate of FET 2 is connected to a voltage VG, presumed in this discussion to be held constant. The drain of FET 2 and first terminal of load capacitor 3 are connected at node 5. The other terminal of load capacitor 3 is connected to circuit common (‘ground’).
FIG. 2 shows voltage waveforms associated with the circuit of FIG. 1. At the beginning of a charge-transfer cycle VX is at a high voltage 21; node 5 has been initialized to a relatively high voltage 23; and node 4 to a lower voltage 22. For this basic explanation, it is assumed that voltage 22 is more positive than VG−VT, where VT is the threshold of FET 2. Under these conditions FET 2 is biased below threshold, so no significant current flows through it.
The charge transfer is initiated at time t1 by lowering VX towards a more negative voltage. Initially, V4, the voltage of node 4, follows VX in a negative direction. At time t2, V4 becomes equal to VG−VT, causing FET 2 to turn on. The resulting current flow through FET 2 limits further negative excursion of V4. At time t3 VX reaches its lower value 24. Current continues to flow through FET 2 into capacitor 1, causing node 4 to charge in a positive direction. As V4 approaches VG−VT, the current through FET 2 diminishes. V4 settles towards VG−VT at a continuously-diminishing rate, reaching voltage 26 at time t4. At t4 VX is returned to its original voltage. This positive-going transition is coupled through capacitor 1 to node 4, causing FET 2 to turn off altogether and ending the charge transfer.
During the events described, current flows from capacitor 3 through FET 2 into capacitor 1. The integral of this current flow constitutes the transferred charge, QT. QT can be expressed in terms of the voltage changes and respective capacitances at VX, node 4, and node 5. Neglecting the device capacitances of FET 2, the charge delivered to capacitor 3 can be expressed in terms of the voltage change across it, using the well-known expression Q=CV. Identifying the capacitance of capacitor 3 as C3 and the voltage change at node 5 as ΔV5, we have:QT=C3ΔV5  Equation 1Note that with the waveforms shown, ΔV5=(voltage 25−voltage 23) is negative, so QT is negative; i.e., it consists of electrons.
QT can also be expressed in terms of the voltage change across capacitor 1. Using similar notation, we have:QT=C1(ΔVX−ΔV4)  Equation 2The relevant voltage changes occur between the beginning and the end of charge transfer; thus, for the waveforms of FIG. 2,ΔVX=(voltage 24−voltage 21)  Equation 3andΔV4=(voltage 26−voltage 22)  Equation 4
For the conditions described, voltage 22 is a constant (it is an initial condition). If node 4 were to settle perfectly to its nominal asymptote VG−VT, which is also a constant, then ΔV4 would be a constant. In that case, Equation 2 could be re-written as:QT=C1ΔVX+(constant)  Equation 5This expression represents an idealization of the charge-transfer operation which is perfectly linear. For the realistic case in which settling of node 4 is imperfect, Equation 2 can be re-formulated as:QT=C1[ΔVX−(voltage 26)]+(constant)  Equation 6From this form it can be seen that any non-linearity or incomplete settling of charge transfer is attributable to voltage 26, the voltage of node 4 at the end of charge-transfer.
Charge-transfer operation essentially similar to that described above is used in all conventional BBDs. Practical details, such as the means of establishing the described initial conditions, realistic clock waveforms, etc. are not pertinent to the present invention and will not be further described here. The same charge-transfer technique is also used to provide charge-packet input in many CCD signal-processing circuits. (Subsequent charge transfers in CCDs use a different principle, not described here.)
The mode of charge-transfer described above will be termed “passive” charge transfer in the following discussion. This term refers to the fact that, during the charge-transfer process, the gate voltage VG applied to FET 2 is static, not actively controlled in response to the charge being transferred. (In practical BBDs, VG is typically clocked rather than static, but it is not responsive to the charge being transferred.) This passive charge transfer process is subject to two important error sources.
The first error source derives from the nature of the settling of node 4 during the t3-to-t4 interval in FIG. 2. During this time, as described above, node 4 is charging in a positive direction, reducing the gate-source voltage of FET 2. This decreasing gate-source voltage causes a decrease in current through the FET. This declining current in turn results in a declining rate of charging of node 4. This process is very non-linear in time, and also depends in a non-linear manner on the size of charge packet being transferred. As a result, the residual voltage 26 in FIG. 2 (and Equation 6) depends non-linearly on QT, resulting in an overall non-linear charge-transfer operation. Moreover, with practical circuit values, the settling time of node 4 is unacceptably long for high-speed circuit operation. Passive charge-transfer is thus both slow and non-linear; in many applications these limitations degrade speed and accuracy unacceptably.
The second error source arises due to the change ΔV5 in FET drain voltage V5. As shown above (Equation 1) this change is proportional to QT. FETs exhibit a feedback effect, in which a variation in drain voltage causes, in effect, a variation in threshold voltage VT. Thus the “final” voltage VG−VT, towards which V4 settles, is not in fact a constant (as in the idealized discussion above) but a function of the charge being transferred. This effect is equivalent to a dependency of voltage 26 on the size of QT: larger |QT| results in a more-negative value of voltage 26. This effect amounts to a charge-transfer gain of less than 100%. It typically includes a small non-linear component as well, exacerbating the non-linearity issue discussed above.